Consider dvs implemented in 0.8 um cmos technology with fox = tom and. lov = 0.1 um a ring oscillator is designed to mimic the critical path in the system using thirteen stages of minimum size inverters with load capacitances at each stage equivalent to six on-chip loads.

a. calculate and plot the ring oscillator frequency as a function of the supply voltage assuming = p = 0.3v for all devices iv sv s 5v
b. calculate and plot the switching power versus the supply voltage for a symmetric inverter in the system. assume the system clock frequency is derived from the ring oscillator, the switching activity is 0.2, and the on- chip fan-out is 6. [25]