1. Consider a direct-mapped cache that can accommodate 8Mbytes from a main memory, that uses a 32-bit address and 32-byte blocks. Assume 4-byte data. (a) Provide format of the address indicating all fields; (b) Provide the cache layout similarly as on Slide H47, excluding gates, multiplexers and comparators; (c) Assuming that CPU generates address 0xABCDE678, - what is the cache entry accessed? - if it is a hit indicate as much as possible of contents for that entry.