In this experiment you will be exposed to the coding of FSM – Finite State Machines using Verilog. The procedure will use the methods you were exposed to in Digital Logic II which allowed you to derive a circuit containing flip-flops and logic gates, then you will describe the circuit using Verilog. Experiment: Each section will receive a problem description which you will design in the lab by following the steps given below. To facilitate your understanding an example will be