For simplicity, assume that the second operation begins after the first completes, even though they are on different processor cores.
for implementation 1,
* the first read generates 50 stall cycles because the read is satisfied by c0’s cache: c1 stalls for 40 cycles while it waits for the block, and c0 stalls for 10 cycles while it writes the block back to memory in response to c1’s request; and
* the second read by c3 generates 100 stall cycles because its miss is satisfied by memory.
therefore, this sequence generates a total of 150 stall cycles.
for the following sequences of operations, how many stall cycles are generated by each implementation?
a) c0: r, ac20
c0: r, ac28
c0: r, ac30
b) c0: r, a00
c0: w, ac08 < - 48
c0: w, ac30 < - 78