Write a Verilog module that describes 8-bit right shifter register with control signals A(arithmetic), L(logical), CLR(clear) and LD(load). Input signals are CLK, LD and 8-bit input D. Output signal is 8-bit output Q. CLR signal will clear Q. LD signal will load input D to Q. A signal will do arithmetic right shift of Q, while L signal will do logical right shift of Q.

Adouble-strand no. 60 roller chain is used to transmit power between a 13-tooth driving sprocket rotating at 300 rev/min and a 52-tooth driven sprocket. a) what is the allowable horsepower of this drive? b) estimate the center-to-center distance if the chain length is 82 pitches. c) estimate the torque and bending force on the driving shaft by the chain if the actual horsepower transmitted is 30 percent less than the corrected (allowable) power.

Determine whether or not it is possible to compress air adiabatically from k to 140 kpa and 400 k. what is the entropy change during this process?

Burgers vector is generally parallel to the dislocation line. a)-true b)-false