Carry generate (G) and carry propagate (P) are defined as follows: G =AB and P = A  B. a) Show the expressions for Sum and Carry-out of a 1-bit Full Adder (1bFA) in terms of Carry-In, P and G. b) Design the 1b FA with any number of 2-to-1 multiplexers and logic gates. Show the schematic with inputs A, B, Carry-in and outputs Sum and Carry-out. c) Estimate the following propagation delays for your schematic: • Carry-in to Carry-out (t1), • Data-to-Carry-out (t2), • Carry-in to sum (t3).Assume the following propagation delays for 2-to-1mux: data D1, DO to output Y: 5 ns; select S to output Y: 10 ns. Assume a 10 ns delay for logic gates, a 5 ns delay for inverters.