Engineering, 06.05.2020 01:35 hector87

Suppose we have a cache that can hold a total of 256 bytes with 4 words per block.

Suppose that the cache is designed as a 4-way set associative cache. Compute the set index, offset, and the tag for the following addresses:

0x00000004

0x00000014

0x01000004

0x00000008

0x00000018

0x01000008

In designing the cache controller, we would like to simplify the division and mod operations required for computing the set index, offset, and tags. Specifically, for the cache design given above, we can partition the 32 bits in the address into three fields, one each for the set index, offset, and the tags. State which bits from the address will be used to compute each of the set index, offset, and the tag.

For each of the addresses given above, give another address that will be mapped to the same set but have a different tag.

Suppose that the cache is now designed as a fully associative cache. Compute the offset and the tag for the same set of addresses.

Need help on the 2,3,4

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Suppose we have a cache that can hold a total of 256 bytes with 4 words per block.

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