Implement the FSM as gates and D Flip-Flops. Use the following binary-encoded state assignments: A=00, B=01, C=10, and D=11. Show all your steps and minimize your logic using K-Maps into sum of products form. Give the final design as a schematic. Assume you do not need inverters for x0 , Q0 1 or Q0 0. (b) Now implement the FSM as gates and D flip-flops using the following one-hot state encoding: A=0001, B=0010, C=0100, D=1000. Show all your steps and give the final design as a schematic. Again implement all your next-state and output logic using sum-of-products form. (But don’t use K-Maps here!) (c) Compare the cost of your solutions in (a) and (b) in terms of the number of flipflops, and the number and size (number of inputs) of the combinational gates. (d) Compute the maximum clock frequency for your solutions from (a) and (b) assuming the following timing characteristics: