The first thing you are going to create is a logical one bit full adder in continuous assignment verilog. You can only use logical operators. Call this module FA1. In this module, you will add in the code to account for the gate delays. There are a few considerations you need to follow to make this adjustment from your base code: You need to include the "timescale" directive at the top of the file, it needs the same values as the one you will use in your test bench You will need to add the time delay notation to each of the assign statements with the following rules: ○ AND operation, a delay of 2 time units ○ OR operation, a delay of 3 time units ○ XOR operation, a delay of 4 time units will occur ○ NAND operation, a delay of 1 time unit will occur ○ NOR operation, a delay of 1.5 time units will occur