Engineering, 20.04.2020 22:35 minecraft56

For the following questions, assume a memory-register ISA, that uses only register addressing and absolute addressing, has 32 different instructions, a word size of 32 bits, 8 word-sized registers, a single instruction encoding format that packs two fixed-length instructions per word, and uses word-addressing.

How many bits are needed to encode the opcode? How many bits are needed to encode the register addresses?
How much memory can be used in this architecture? What if byte-addressing was used instead?
What would be the instruction encoding format? Assuming only 6 of the 32 instructions encoded two operands, design an instruction encoding using two formats, that allows you to increase the size of the operands for these instructions.
If the change you made in Q6 is used to increase the number of registers, how many registers could you add?
With the change you made in Q6, how many opcode encodings remain unused?
If register indirect addressing mode was added, how much memory could be addressed?

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For the following questions, assume a memory-register ISA, that uses only register addressing and ab...

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