A Binary Adder can be designed as a parallel or serial adder with accumulation. For this

experiment, the parallel adder will be designed to add two binary digits, three bits each,

X (expressed as X2X1X0) and Y (expressed as Y2Y1Y0). The adder can be designed via

the "brute force" method in which three, six variable Karnaugh maps are used to

implement the functions representing the outputs of a three-bit addition. However, this

method is not the most efficient so a different design approach, called the iterative cell

technique, will be used. In the iterative cell technique, two binary numbers are presented

in parallel to the cell as inputs. The rightmost cell adds the least significant bit X0 and Y0

to form a sum digit S0 and carry digit C0. The next cell adds the carry C0 to bits X1 and Y1

to form a sum digit S1 and a carry digit C1. The last cell adds the carry C1 to bits X2 and

Y2 to form a sum digit S2 and a carry digit Cout.

To design a network, a typical cell should be designed which adds a carry Ci to bits Xi

and Yi to generate a sum digit Si and a new carry Cout as shown below. The circuit that

realizes this function is referred to as a full adder cell. Please note that the operation on

the least significant bits of X and Y does not include a carry-in signal. Thus a half adder

circuit can be used for the rightmost cell. The diagrams below illustrate the functional

blocks for a one-bit full adder and a one-bit half adder.

Prepare and complete a truth table for the full adder cell. Transfer this information to

a Karnaugh Map and obtain minimum expressions in both sum of products and

product of sums forms.

Use Boolean algebra to reduce sum of products expression to a more workable

expression. (i. e. XOR