Consider the following three pipeline processor implementations. Assume that all 3 pipelines can achieve a CPI of 1, except for mispredicted branches . Implementation X: A pipeline length of 20 stages with branches resolving in stage 7, running . Implementation Y: A pipeline length of 30 stages with branches resolving in stage 12, Implementation Z: A pipeline length of 25 stages with branches resolving in stage 5, running For all processors, the branch predictor is located in stage 1 a) What are the cycle times for each of these pipelines, in nanoseconds? at 666MHz running at 1GHz. at 833MHz. b) Now consider that you are the CTO at Intel and you want to choose a pipeline implementation for your next generation processor. You know that the branch predictor in your architecture can achieve 95% prediction accuracy. If you were to select a pipeline design purely based upon on minimum branch misprediction penalty in nano-seconds, which architecture would you choose? c) Now, consider pipeline Implementation X. Assume this is the only pipeline available to you, and as CTO you have two choices. The next generation of silicon technology has given you extra transistors to work with, and you can either use them to build a better branch predictor that will achieve 98% accuracy instead of 95%, OR to build extra hardware to allow branches to resolve in stage 5 instead of stage 7. Which approach will provide the best average CPl for a workload with 20% branches?