Design a multiple-output logic circuit whose input is a BCD digit and whose outputs are defined as follows: 1f: Detects input digits that are divisible by 4, 2f: Detects numbers greater than or equal to 3, 3f: Detects numbers less than 7. Write a Verilog and/or VHDL model of the circuit. Also, realize the circuit using NAND gates.

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answer:

1.3 + 20

explanation:

20.1.3