The purpose of this lab is to learn how to design a simple combinational logic network. in part i, you will enter your design in quartus as two different schematics and simulate them using modelsim-altera. then you will verify one of the circuits on the de10-lite board using the switches and hex0 seven-segment display. in part ii, you will add a counter to your design that will be clocked by a pushbutton. you will again verify the design on the de10-lite board.