Write behavioral vhdl code that implements the state machine that you designed in the previous module. use a case statement to represent the state table as illustrated in the figure below. use two processes – one for the combinational logic and one for the state register. add an asynchronous reset input.

1 entity sm17_2 is

2 port(x, clk: in bit;

3 z: out bit);

4 end sm17_2;

5 architecture table of sm17_2 is

6 signal state, nextstate: integer range 0 to 6: = 0;

7 begin

8 process(state, x) --combinational cicuit

9 begin

10 case state is

11 when 0=>

12 if x='0' then z< ='1'; nextstate< =1;

13 else z< ='0'; nextstate< =2; end if;

14 when 1=>

15 if x='0' then z< ='1'; nextstate< =3

16 else z< ='0'; nextstate< =4; end if;

17 when 2=>

18 if x='0' then z< ='0'; nextstate< =4

19 else z< ='1'; nextstate< =4; end if;

20 when 3=>

21 if x='0' then z< ='0'; nextstate< =5

22 else z< ='1'; nextstate< =5; end if;

23 when 4=>

24 if x='0' then z< ='1'; nextstate< =5

25 else z< ='0'; nextstate< =6; end if;

26 when 5=>

27 if x='0' then z< ='0'; nextstate< =0

28 else z< ='1'; nextstate< =0; end if;

29 when 6=>

30 z< ='1'; nextstate< =0;

31 end case;

32 end process;

33 process (clk) --state register

34 begin

35 if clk'event and clk='1' then --rising edge of clock

36 state< =nextstate;

37 end if;

38 end process;

39 end table;

2. simulate the vhdl code and verify that it works correctly. use the same test sequences that you used in your assignment in the previous module.

3. synthesize the vhdl code and download it to the basys 3 hardware board for testing. use the vivado software for synthesizing the code and programming the fpga.

4. verify the correct operation of the hardware implementation of the state machine using the same procedures as in the previous module. submit your vhdl code in this activity.