Based on your design from lab #6 (design of a decimal-number-to-braille encoder), write a verilog hdl module describing the decimal-to-braille encoder. use the same logic expressions (in terms of and, or, and not gates), as well as the same input and output names. add your assign statements to the header provided in the "supplementary materials" folder on blackboard, specifically the "asic world - verilog hdl tutorial and examples" and "introduction to verilog - p. m. nyasulu " should . hint: you should have 4 assign statements.