Design an 8-bit shift-up register with a single input for the new low order bit. your shift register should have an asynchronous clear. write verilog code (either structural or behavioral – you need not write both) to simulate the register. use bus notation for the 8-bit output. write a testbench. you will need to create a clock in the testbench, as well as provide test inputs for your shift input and for your clear. you may either include your test inputs inside your clock loop or write two initial begin . . end blocks – one for your clock and one for your test inputs.