Consider doubling the clock speed of the standard five-stage pipeline, with full register forwarding, by doubling its depth. Each stage of the five-stage pipeline would be split into two stages in the deeper pipeline. Assume a typical workload where loads, ALU instructions, and branches, respectively, account for 1/4, 1/2, and 1/6 of all instructions, and other types of instructions cover the rest. Further, 40% of all ALU instructions and loads have a dependent arithmetic instruction immediately following each of them; the rest 60% have an abundant number of independent arithmetic instructions following each of them. Branches are resolved in MEM (not in Decode). The pipeline employs branch prediction which has 90% accuracy. There are no other dependencies. If the ideal CPI ignoring dependencies is 1, (a) what are the execution times of the above workload on the five-stage pipeline and ten-stage pipeline, and (b) the net speedup of the deeper pipeline