Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding(or bypassing) hardware. Use a pipeline timing chart like that shown in the textbook Figure C.5.Assume that the branch is handled by predicting it as not taken and that the branch outcomesand targets are known (including the PC update) by the end of the decode stage. If all memoryreferences take 1 cycle, how many cycles does this loop take to execute? Justify your answer.