Assume time for the MIPS stages are the following: a. 200ps for register read or write
b. 600ps for other stages
Calculate the total time for each instruction for the single-cycle (non-pipelined) MIPS architecture Instruction Instruction fetch Register Read Total Time ALU op Memory Access Register Write
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instruction 7
Instruction 8
Instruction 9
Instruction 10
Instruction 1: lw $1,100 ($5)
Instruction 2: sw $3,200 ($10)
Instruction 3: add $4, $10, $12
Instruction 4: beq $9, $4, 100
Instruction 5: xor $8, $6, $3
Instruction 6: add $4, $2, $1
Instruction 7: sub $2, $6, $7
Instruction 8: addu $7, $8, $9
Instruction 9: subu $2, $1, $5
Instruction 10: bne $18, $19, L2