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For a processor with a base CPI (ideal cache) of 1.0, an ICache miss rate of 1.0%, a DCache miss rate of 5%, an instruction mix of 30% loads and stores, and a miss penalty of 250 cycles to main memory (give answers in decimal or x%) Required:
a. What is the per-instruction miss rate?
b. What is the effective (overall) CPI (CPI including cache misses)?

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