Assume that the pipelined processor is not using forwarding. Also, assume that register writes happen during the first half cycle and register reads happen during the next half cycle. Draw a pipeline diagram for the instruction sequence below, showing the flow of instructions through the pipeline during each clock cycle. Indicate any necessary stalls on the pipeline diagram. add $3, $2, $1lw $4, 8($3)sub $5, $3, $4lw $6, 12($3)sw $4, 20($5)bne $4, $6, 8