assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write- back) and the code given below. all ops are one cycle except lw and sw, which are 1 2 cycles, and branches, which are 1 1 cycles. there is no forwarding. show the phases of each instruction per clock cycle for one iteration of the loop.

Hello the loop required for your question is missing below is the loop

Loop: lw x1,0(x2)

     addi x1,x1, 1

     sw x1,0(x2)

     addi x2,x2,4

     sub x4,x3,x2

 bnz x4,Loop

answer : attached below

Explanation:

Show the phases of each instruction per clock cycle for one iteration of the loop

                                                               loop length

       loop                                            

     lw x1,0(x2)

 addi x1,x1, 1 values attached below

     sw x1,0(x2)

     addi x2,x2,4

     sub x4,x3,x2

     bnz x4,Loop

Attached below are the phases of each instruction per clock cycle for one iteration of the loop

there is no (:

answer is c. complication