Below is Verilog code for the modules top and tangled. Write down its minimal expressions for the outputs top in terms of its inputs. module top ( input a, b,c, d,e, f,
output x, y,z, w,v );

tangled mess (.boo({a, b,c, d}), .foo({e, f}), .goo({x, y,z, w}), .moo(v));

endmodule

module tangled ( input [3:0] boo,
input [1:0] foo,
output [3:0] goo,
output moo);

wire [7:0] web, spy;

assign web = {boo, foo, boo[3:2]};
assign spy = web & 8'd119;
assign goo = { &spy[3:0], |web[6:2], web[7], spy[5]};
assign moo = ~|(web ^ spy);

endmodule