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Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

Consider a direct-mapped cache with 216 words in main memory. the cache has 16 blocks of 8 words each. it is a word-addressable computer (rather than a byte-addressable computer which we normally discuss). (a) how many blocks of main memory are there? (b) what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, cache block, and block offset fields (if they apply)? (c) to which cache block will the memory reference db6316 map?

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