It is required to design and implement: 1. A counter which counts from 0 to 255 with seven segment display. 2. A logic function y=∑( 0,3,5,10,16,20,30 35). 3. Summing and subtracting circuit of 8 digit numbers. 4. ROM (a, b,c, d) to 60 to 75 in binary. 5. A timing module which counts time in us or ms or seconds.

Acomputer has a two-level cache. suppose that 60% of the memory references hit on the first level cache, 35% hit on the second level, and 5% miss. the access times are 5 nsec, 15 nsec, and 60 nsec, respectively, where the times for the level 2 cache and memory start counting at the moment it is known that they are needed (e.g., a level 2 cache access does not even start until the level 1 cache miss occurs). what is the average access time?