Cyclic Redundancy Check (CRC) is an effective error detection mechanism. Suppose you have data bits of 10010011011 and divisor is 10011. As per the given information, what is encoding bits at the sender side? Similarly, at the receiver end ensure syndrome value is zero. Follow all necessary steps to complete calculation at both ends

The appended bits are 1100, the sender sending the data after adding is 100100110111100.

Note: Kindly find an attached document to part of the solution for the  necessary steps to the complete calculation at both ends is attached  below.

Explanation:

Solution

Given that:

We have the data bits of 10010011011 and the divisor is 10011

Thus,

We have to append four 0's at the end of data bits

The appended bits are 1100

At the receiver side the bits are 0000

Therefore sender sending the data after adding is 100100110111100

answer; ///400 ibs;