Suppose we wanted to add the auto decrement addressing mode to the MIPS ISA – e. g. lw R1, 100(R2--). This saves an instruction every time we observe a load followed by a decrement of the address register. Is this a good idea? Consider only performance, and assume that we have to increase cycle time by 11% to accommodate the new instruction, that 15% of our instructions are loads, that we can apply this change to 42% of all loads, and that the CPI doesn’t change.