Consider the following assembly language code:

I0: lw $s2, 0($s0)
I1: addi $s3, $s2, 4
I2: slt $t0, $s0, $s1
I3: add $t1, $t0, $s0
I4: sub $t4, $t1, $s2
I5: lw $t4, 100($s0)
I6: and $s0, $t0, $s3
I7: w $t5, 0($t1)

For each instruction, identify whether or not a hazard should be detected. If so, identify the type of hazard as structure, data, or control. Assume the instructions are being processed on a MIPS pipelined datapath without forwarding.

See explaination

Explanation:

Given that:

Consider the MIPS assembly language code segment given below.

I1: addi $s3, $s2, 5

I2: sub $s1, $s3, $s4

I3: add $s3, $s3, $s1

I4: Iw $s2, 0($s3)

I5: sub $s2, $s2, $s4

I6: sw $s2, 200($s3)

I7: add $s2, $s2, $s4

(a) Identify the data dependency in the following code:

RAW - Read after write: This dependency occurs when instruction I2 tries to read register before instruction I1 writes it.

WAW - Write after write: This dependency occurs when instruction I2 tries to write register before instruction I1 writes it

• Read after write (RAW)

I1: addi $s3, $s2, 5

I2: sub $s1, $s3, $s4

• Read after write (RAW)

I2: sub $s1, $s3, $s4

I3: add $s3, $s3, $s1

• Write after write (WAW)

I4: lw $s2, 0($s3)

I5: sub $s2, $s2, $s4

• Read after write (RAW)

I5: sub $s2, $s2, $s4

I6: sw $s2, 200($s3)

(b) Data hazards which can be solved by forwarding:

(1) Read after write (RAW)

I1: addi $s3, $s2, 5

I2: sub $s1, $s3, $s4

addi $s3, $s2,5 IF ID EXE MEM WB

sub $51, $s3, $s4 IF ID EXE MEM WB

(2) Read after write (RAW)

I2: sub $s1, $s3, $s4

I3: add $s3, $s3, $s1

sub $51, $s3. $54 IF | ID EXE |MEM WB

add $s3, $s3, $s1 IF | ID EXE | MEM | WB

(3) Read after write (RAW)

I5: sub $s2, $s2, $s4

I6: sw $s2, 200($s3)

sub $52, $s2, $54 IF ID |EXE MEM | WB

sw $52, 200($s3) IF ID EXE MEM WB

(c) Data hazards which can lead to pipeline stall:

• Write after write (WAW)

I4: lw $s2, 0($s3)

I5: sub $s2, $s2, $s4

lw $s2, 0($s3) IF ID EXE MEM WB

sub $s2, $s2, $s4 IF ID Stall EXE | MEM | WB