1. What is the CPI for a single cycle process model?
Use the following for problems 2 through 6:
• memory read/writes take 200 ps
• ALU/adder operations take 100 ps
• (each) register read/writes take 75 ps.
2. Assume a processor only fetches instructions (in other words, there is no execution of the instructions). Assuming no additional delays, how long is the clock cycle for a single cycle implementation and a fixed-length clock?
3. Assume a processor is only able to support register addressing mode instructions Assuming no additional delays, how long is the clock cycle for a single cycle implementation and a fixed-length clock?
4. Assume a processor is only able to support pc-relative addressing mode instructions Assuming no additional delays, how long is the clock cycle for a single cycle implementation and a fixed-length clock?
5. Assume a processor is only able to support pseudo-direct addressing mode instructions. Assuming no additional delays, how long is the clock cycle for a single cycle implementation and a fixed-length clock?
6. Assume a processor supports all instructions and addressing modes. A program consists of 25% store words, 15% load words, 10% branches, 5% jumps and 45% alu operations. Assuming no additional delays, how long is the clock cycle for a single cycle implementation and a fixed-length clock?
7. The control line values are given in the notes and in your text. For each of the instructions listed (r-type, lw, sw, beq), describe the effect that a single stuck-at-0 fault (the value is always 0) occurs for each of the 9 control lines. For example RegDst is stuck at 0, but the other control lines have the correct value. Which instruction will not work correctly and why?
8. Give the control for the 9 control lines to implement the addi instruction.