Consider a 2-way set-associative 32 byte cache for an 8-bit system. Each block is 8 bytes and an LRU eviction policy is used. Given the following sequence of cache accesses, determine whether each access is a hit or a miss and then classify each of the misses as one of compulsory, capacity, or conflict.
Additionally, break down each address to show the tag in order to help see what is in the cache. Please follow the format of the first row (which is filled out for you).

Address Tag Hit/Miss Compulsory Capacity Conflict
0x16 0x5 Miss X
0x14
0x34
0x15
0x26
0x35
0x27
0x06
0x01
0x09

In the given proble, we have 8B cache. One block consists of 2 Bytes, so, there are total of 4 blocks in the cache. It is given that the memory is 2 way set associative, this means, each set consists of 2 blocks. So, there are 2 sets in the cache. Block offset will require 1 bit as there are 2 B in a block. Set number will require 1 bit as there are only two sets in the cache. Here is the structure of the address:

Tag(6 bits)         set number(1 bit)    Block offset(1 bit)

from the above structure, we can determine the required tag field of the table. To decide whether it is a miss or hit, we will see if the given block is already present in the memory. When a block enters the memory for he first time, it is a compulsory miss. A miss said to be capacity miss if cache is full and there is no way to avoid the miss. A miss is conflict miss if it could have been avoided by not replacing this block earlier with some other block.

Explanation:

See filled table below

a.s= 230t– 110; 1500 lbc.t= 230s– 110; 1500 lbb.s= 230t+ 110; 1720 lbd.s= 199t– 110; 1280 lb

answerstandard;