Show how the same four instructions move through each stage of the five stage pipeline, similar to the example on slide 13 of lecture 17. This pipeline does support bypassing. Make sure the decode stage does not advance an instruction through the pipeline unless all data dependences are correctly resolved. You don't need to show the latch involved in every bypass (but feel free to ponder this question for your own understanding). (25 points)
I1: add $s1, $s2, $s3
I2: lw $s4, 4($s4)
I3: add $s5, $s4, $s1
I4: sw $s5, 8($s2)

See explaination.

Explanation:

In the instruction three add needs values $s4 and $s1 the value of $s1 is available but $s4 value not available so we need to bypass the value 2nd instruction to 3rd instruction by using MEM/WB buffer which is present in between MEM and WB stage in the pipeline similarly in the 4th instruction also $s5 value has to bypass the value from 3th instruction to 4thinstruction.

Go to attachment for image.

Instructions Add $s1,Ss2,$s3IF Lw $s4,4(Ss4) Add $s5,$s4,$s1 Sw $s5,8($s2) 2 3 4 MEMWB EX IF IID MEMWB IF ID EX MEMWB IF ID M4 instruction can complete its execution in 5 clock cycle by using bypassing features. if bypassing feature is not there it required grater than 8 cycles

the answers

1. video

2. net

3. cloud

4. optical

5. rambus

hope it