You are given the following code snippet which executes on a 5-stage pipelined processor. How many cycles does the code take to execute, if no data bypassing is implemented ?

addi $s1, $0, 10
lw $t0, 4($s0)
srl $t1, $t0, 1
add $t2, $t1, $s1
sw $t2, 4($s0)

a. 5
b. 9
c. 10
d. 14

5-Stage Pipeline Diagram for given set of instructions is given below. From the table we get to know that given code snippet need 14 clock cycles to execute with 5 stage pipelines without bypassing technique.

Option: (d)

Explanation:

If there is hazard on one instruction immediately after load/store or memory instructions then there is more delay than usual. So, we use two stalls for hazard present immediately after load instruction i.e. instruction 2.

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