We will now add support for register-memory ALU operations tothe classic five-stage RISC pipeline. To offset this increase incomplexity, all memory addressing will be restricted to registerindirect (i. e., all addresses are simply a value held in aregister: no offset or displacement may be added to the registervalue). For example, the register-memory instruction ADD R4, R5,(R1) means add the contents of register R5 to the contents of thememory location with address equal to the value in register R1 andput the sum in register R4. Register-register ALU operations areunchanged. Answer the following for the integer RISCpipeline.
a. List a rearranged order of the five traditional stages ofthe RISC pipeline that will support register-memory operationsimplemented exclusively by register indirect addressing.
b. Describe what new forwarding paths are needed for therearranged pipeline by stating the source, destination, andinformation transferred on each needed new path.
c. For the reordered stages of the RISC pipeline, what newdata hazards are created by this addressing mode? Give aninstruction sequence illustrating each new hazard.
d. List all ways that the RISC pipeline with register-memory. ALU operations can have a different instruction count for a givenprogram than the original RISC pipeline. Give a pair of specificinstruction sequences, one for the original pipeline and one forthe rearranged pipeline, to illustrate each way.
e. Assume all instructions take 1 clock cycle per stage. Listall ways that the register-memory RISC can have a different CPI fora given program as compared to the orginal RISC pipeline.