You are designing a write buffer between a write-through L1 cache and a write-back L2 cache. The L2 cache write data bus is 16 B wide and can perform a write to an independent cache address every four processor cycles.

a. How many bytes wide should each write buffer entry be?
b. What speedup could be expected in the steady state by using a merging write buffer instead of a non-merging buffer when zeroing memory by the execution of 64-bit stores if all other instructions could be issued in parallel with the stores and the blocks are present in the L2 cache?
c. What would be the effect of possible L1 misses on the number of required write buffer entries for systems with blocking and non-blocking caches?

Jason, samantha, ravi, sheila, and ankit are preparing for an upcoming marathon. each day of the week, they run a certain number of miles and write them into a notebook. at the end of the week, they would like to know the number of miles run each day, the total miles for the week, and average miles run each day. write a program to them analyze their data. your program must contain parallel arrays: an array to store the names of the runners and a two-dimensional array of five rows and seven columns to store the number of miles run by each runner each day. furthermore, your program must contain at least the following functions: a function to read and store the runners’ names and the numbers of miles run each day; a function to find the total miles run by each runner and the average number of miles run each day; and a function to output the results. (you may assume that the input data is stored in a file and each line of data is in the following form: runnername milesday1 milesday2 milesday3 milesday4 milesday5 milesday6 milesday7.)

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What does the level 1 topic in a word outline become in powerpoint? a. first-level bullet item b. slide title c. third-level bullet item d. second-level bullet item