Problem 3: (6 pts) Direct memory access is used for high-speed I/O devices in order to avoid increasing the CPU’s execution load. a. How does the CPU interface with the device to coordinate the transfer? b. How does the CPU know when the memory operations are complete? c. The CPU is allowed to execute other programs while the DMA controller is transferring data. Does this process interfere with the execution of user programs? If so, describe what forms of interference are caused.

Explanation:

a)  The CPU can initiate a DMA operation by writing values into special registers  (I/O ports, or memory-mapped I/O registers, depending on the system design) that can be independently accessed by the device.  The device initiates when these registers are written-to, and will take the appropriate action.

b) When the device is finished with its operation, it could write to a special register or interrupts the CPU  to indicate the completion of the operation.

c) Both the device and the CPU will compete for cycles on the memory bus simultaneously.  The memory controller provides access to the memory bus in a fair manner to these two entities.  A CPU might therefore be unable to issue memory operations at peak speeds since it has to compete with the device in order to obtain access to the memory bus. Also, any CPU program that would be capable of using all the memory bus cycles could run more slowly while the DMA is active.

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