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Computers and Technology, 14.02.2020 19:58 emmanuelcampbel
Caches are commonly implemented in SRAM, and the cache layout impacts the total amount of SRAM required to implement the cache. For the following two problems, assume the caches are byte addressable and addresses and data words are both 32 bits. a. How many total bits are required to implement a 128 KiB direct-mapped cache with 4-word blocks? b. How many total bits are required to implement a 128 KiB direct-mapped cache with 32-word blocks?
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