Write a verilog code that implement the following instructions to verify the correctness of your pipelined cpu design. the code should be used to initialize the instruction memoryblock. the register file should be all initialized to zeros. in the test program, it is aimed to check the 20 instructions. the main part of the test program is a subroutine in which four32-bitmemory words are summed by a forloop. after returning from the subroutine, the sum is stored in the data memory by a swinstruction. a code pattern that causes pipeline stall is also prepared within the loop. word address is used to assign the content of each word (a 32-bit instruction). the parenthesized hexadecimal number in the center of each line is the byte address (pc).