Problem 2 (20 points) assume that your application has 400 data reads for each 8,000 instructions. for the same number of instructions the application has 100 data writes. the cache used has an instruction miss rate of 0.6% and a data cache miss rate of 6%. each block size has 32 bytes of data. a) if the cpu that uses this cache has a cpi of 2 with write-through write-allocate to dram, and each miss generates a request for a block, what are the needed read and write bandwidths (bytes/cycle) when communicating with dram? b) this time the cpu with the same cpi has a write-back, write allocate cache. on average 20% of the blocks that need to be replaced are dirty. what read and write bandwidths are needed in this case?