In this question we examine how resource hazards, control hazards, and instruction set architecture (isa) design can affect pipelined execution. problems in this exercise refer to the following fragment of mips
code
sw r16,12(r6)
lw r16,8(r6)
beq r5,r4,label #assume r4=! 4
add r5,r1,r4
slt r5,r15,r4

pipeline latencies:
if id ex mem wb
200 120 150 190 100ps

for this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. if we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. to guarantee forward progress, this hazard must always be resolved in favor ofthe instruction that accesses data. what is the total execution time of this instruction sequence in the 5- stage pipeline that only has one memory? we have seen that data hazards can be eliminated by adding nops to the code. can you do the same with this structural hazard? why?