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< §§5.3, 5.8> suppose a cpu with a write-through, write-allocate cache achieves a cpi of 2. what are the read and write bandwidths (measured by bytes per cycle) between ram and the cache? (assume each miss generates a request for one block.) 5.7.2 [10] < §§5.3, 5.8> for a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a cpi of 2?

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