Different instructions utilize different hardware blocks in the basic single-cycle implementation. the next three questions refer to the following instructions:

instruction interpretation
a sub rd, rs, rt reg[rd] = reg[rs] - reg[rt]
b lw rt, offs(rs) reg[rt] = mem[reg[rs]+offs]
1) what are the values of the control signals generated by the control in the figure above for each instruction?
2) which resources (blocks) perform a useful function for this instruction?
3) which resources (blocks) produce outputs, but their outputs are not used for this instruction? which resources produce no outputs for this instruction?

different execution units and blocks of digital logic have different latencies (time needed to do their work). in the figure above there are seven kinds of major blocks. latencies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. for the remaining two questions, assume the following
resource latencies:

imem mux alu reg dmem control branch
750ps 50ps 250ps 300ps 500ps 300ps 100ps
4) what is the critical path for an mips sub instruction, and what is the total latency?
5) what is the critical path for an mips beq instruction, and what is the total latency?