(a) (20 points) design a 4-bit cla module. your module must have the following format. submit your verilog code. convince yourself that the code is working correctly with test cases. module cla(g0, p0, g1, p1, g2, p2, g3, p3, cin, c1, c2, c3, c4, g, p); input g0, p0, g1, p1, g2, p2, g3, p3; // generate and propagate signals corresponding to each bit. input cin; // carry-in input output c1, c2, c3, c4; // carry bits computed by the cla. output g, p; // block generate and block propagate to be used by clas at a // higher level.