Following specifications, what is the size of l2 cache that achieves the lowest energy for the pmd (core, l1, l2, memory) for that given task? a. the core frequency is 1 ghz, and the l1 has an mpki of 100. b. a 256 kb l2 has a latency of 10 cycles, an mpki of 20, a background power of 0.2 w, and each l2 access consumes 0.5 nj. c. a 1 mb l2 has a latency of 20 cycles, an mpki of 10, a background power of 0.8 w, and each l2 access consumes 0.7 nj. d. the memory system has an average latency of 100 cycles, a background power of 0.5 w, and each memory access consumes 35 nj.