Given an unpipelined processor with a 10 ns cycle time and pipeline latches with 0.5 ns latency, what are the cycle times of pipelined versions of the processor with 2, 4, 8, and 16 stages if the datapath logic is evenly divided among the pipeline stages? also, what is the latency of each of the pipelined versions of the processor? the latency of a pipeline is the amount of time that single instruction takes to pass through the pipeline, which is the product of the number of pipeline stages and the clock cycle time.