Imagine that you have designed and built a 3-bit counter (outputs q2,q1,q0) that cycles through the states 0-6-3-5-2 and repeats (and that the unused states 1, 4, and 7 immediately return to 0). now the instructor wants you to modify the count to drop the last state (i. e. count 0-6-3-5-0- clearly you will need to redesign and possibly rebuild some of your next state logic. assuming that you used d flip flops for the design, which inputs need to be redesigned?